1. Field of the Invention
The present invention relates to a clock signal generation circuit for generating a clock signal corresponding to a preset frequency, and also relates to a clock signal generation control circuit for controlling an oscillating circuit so that the oscillating circuit generates a clock signal corresponding to a preset frequency.
2. Description of the Related Art
The following description sets forth the inventor's knowledge of related art and problems therein and should not be construed as an admission of knowledge in the prior art.
FIG. 6 is a block diagram of a digital clock signal generation circuit 100 according to the related art. This clock signal generation circuit 100 includes an oscillating circuit 122, a counter 104, a central processing unit (CPU) 130, and a digital-analog converter (DAC) 116.
The oscillating circuit 122 is configured to generate a clock signal CLK having a preset frequency in accordance with a control signal outputted from the digital-analog converter (DAC) 116. This oscillating circuit 122 can be constituted by, for example, a voltage-controlled oscillator (VCO) and generates a clock signal having a frequency corresponding to a voltage signal outputted from the digital-analog converter (DAC) 116.
The counter 104 counts the pulse number of the clock signal outputted from the oscillating circuit 122. This counter 104 counts the pulse number inputted in, for example, one second under the control of a control circuit (not illustrated) and outputs the count value to the central processing unit (CPU) 130.
The central processing unit (CPU) 130 includes a register 132 for storing the preset value of the clock frequency and outputs a digital control signal for controlling the oscillating circuit 122 based on the count value outputted from the counter 104 and the preset value stored in the register 132. The central processing unit (CPU) 130 calculates, for example, the difference between the count value outputted from the counter 104 and the preset value stored in the register 132 and generates a control signal corresponding to the difference. Also, the central processing unit (CPU) 130 is configured to control the operation of various peripheral circuits (not illustrated) connected to the clock signal generation circuit 100 based on a predetermined control program.
A digital-analog converter (DAC) 116 converts the digital control signal outputted from the central processing unit (CPU) 130 into an analog signal and outputs the converted analog signal to the oscillating circuit 122.
As explained above, the clock signal generation circuit 100 is a digital clock signal generation circuit in which the counter 104 counts the pulse number of the clock signal and the central processing unit (CPU) 130 generates a control signal based on the count value.
FIG. 7 shows a block diagram of an analog type clock signal generation circuit 200 according to the related art. This clock signal generation circuit 200 includes an oscillating circuit 222, a frequency dividing circuit 208, a phase comparison circuit 202, a charge pump circuit (CP) 204, and a low pass filter (LPF) 206.
The oscillating circuit 222 generates a clock signal having a predetermined frequency depending on the control signal outputted from the low pass filter (LPF) 206. The oscillating circuit 222 can be constituted by, for example, a voltage-controlled oscillator and generates a clock signal CLK in accordance with the voltage signal outputted form the low pass filter (LPF) 206.
The frequency dividing circuit 208 divides the clock signal CLK outputted from the oscillating circuit 222 and outputs the signal to a phase comparison circuit 202. The phase comparison circuit 202 compares the clock signal outputted from the frequency dividing circuit 208 and a reference clock signal, and outputs the comparison result to the charge pump circuit (CP) 204 which will be detailed below. The reference clock signal can be, for example, a clock signal outputted from a crystal oscillator (not illustrated). This clock signal generation circuit 200 generates a clock signal corresponding to the frequency of the reference clock signal and the frequency division setting of the frequency dividing circuit 208.
Based on the comparison result of the phase comparison circuit 202, the charge pump circuit (CP) 204 selectively outputs a high-level voltage signal (e.g., 3.3 V) or a low-level voltage signal (e.g., 0 V).
The low pass filter (LPF) 206 includes a resistor element R and a capacitor C. One end terminal of the resistor element R is connected to the charge pump circuit (CP) 204 and the other end thereof is connected to the oscillating circuit 222. One end terminal of the capacitor C is connected to the connection point of the oscillating circuit 222 and the resistor element R, and the other end thereof is connected to the ground. This low pass filter (LPF) 206 smoothes the pulse signal outputted from the charge pump circuit (CP) 204 and outputs the smoothed signal to the oscillating circuit 222.
As explained above, this clock signal generation circuit 200 is an analog type clock signal generation circuit that generates a control signal by the charge pump circuit (CP) 204 and the low pass filter (LPF) 206 based on the comparison result of the phase comparison circuit 202.
In the case of using the clock signal generation circuit 100 shown in FIG. 6, the central processing unit (CPU) 130 controls the frequency of the clock signal outputted from the oscillating circuit 122, resulting in increased burden of the central processing unit (CPU) 130. That is, since the central processing unit (CPU) 130 also controls operation of the peripheral circuits connected to the clock signal generation circuit 100, as the load increases, the operation speed of the entire system having the clock signal generation circuit 100 will be deteriorated.
As a method for decreasing the burden of the central processing unit (CPU), it can be considered to use a clock signal generation circuit 200 as shown in FIG. 7. This clock signal generation circuit 200 is an analog type clock signal generation circuit and therefore the frequency of the clock signal can be controlled without using a central processing unit CPU. In the case of generating a clock signal having a relatively low frequency (e.g., 40 kHz), it is required to use a high capacitance capacitor C or a large-resistance resistor R constituting the low pass filter (LPF) 206. This increases the size of the capacitor C and/or that of the resistor R, which in turn increases the size of the clock signal generation circuit 200 and/or the size of the system mounting the clock signal generation circuit 200.
The description herein of advantages and disadvantages of various features, embodiments, methods, and apparatus disclosed in other publications is in no way intended to limit the present invention. For example, certain features of the preferred embodiments of the invention may be capable of overcoming certain disadvantages and/or providing certain advantages, such as, e.g., disadvantages and/or advantages discussed herein, while retaining some or all of the features, embodiments, methods, and apparatus disclosed therein.